On Sunday, Armstrong Subero — an embedded systems engineer from Trinidad and Tobago who describes himself, without irony, as a “third world engineer” — published a rebuttal to Dmitry Grinberg’s sprawling critique of the RISC-V instruction set architecture. Grinberg’s piece, “RISC-V: They Should Have Known Better,” had spent the week climbing Hacker News and Lobsters, earning a reputation as the most substantial technical takedown of the open ISA in years. Subero’s response argued that Grinberg’s obsession with elegance missed the point: for engineers outside the first world, RISC-V’s openness — the ability to use an ISA without licensing fees, without corporate relationships, without being in the right country — matters more than whether the instruction encoding is pretty.
By Monday morning, Subero’s post had 451 points and 234 comments on Hacker News. It was the front-page rebuttal the debate needed.
And then the site went down.
A 429 error. “You have exceeded the allowed number of requests.” The most important voice in the most important argument about open hardware couldn’t keep his blog up when the first world finally paid attention.
The Debate Everyone Is Having
Grinberg’s critique is technical and, by most accounts, substantial. He argues that RISC-V’s design is inelegant — that the committee process produced an ISA with warts, that the instruction encoding is awkward, that the privilege model is muddled. The HN thread is full of emulator authors and compiler writers nodding along, trading war stories about how annoying RISC-V is to implement.
Subero’s response is different. He doesn’t dispute the technical criticisms. He argues they’re beside the point. “The word privilege he tosses around in his article also extends beyond the ISA depending on where you are in the world,” he writes. For an engineer in Trinidad, the choice isn’t between an elegant ISA and an ugly one. It’s between an ISA you can actually use and one you can’t afford to license.
That’s the debate everyone is having: elegance versus access. It’s a good debate. It’s also the wrong one.
The 429 Error Is the Story
Here’s what actually happened this week. A first-world engineer wrote a long, technically sophisticated critique of an open hardware standard. A third-world engineer wrote a rebuttal arguing that the standard’s openness is what makes it valuable. The rebuttal went viral. And the rebuttal’s author — the person making the case for openness — couldn’t keep his website online because his hosting plan couldn’t handle 500 requests per minute.
That’s not a footnote. That’s the whole argument.
RISC-V is open. The ISA specification is freely available. Anyone can implement it. But the ecosystem around RISC-V — the blogs, the documentation, the community forums, the toolchains — runs on the same fragile, centralized, rate-limited infrastructure as everything else on the internet. The “third world engineer” who argues for open hardware can’t even publish his argument without hitting a traffic limit imposed by his web host.
Openness without infrastructure is just philosophy. And the infrastructure of the open hardware movement is, at this moment, a shared hosting plan that buckles under the weight of a single Hacker News front-page appearance.
What Actually Constrains Engineers
The HN thread will spend the week litigating whether RISC-V’s instruction encoding is elegant. That’s a luxury. The actual constraint for most of the world’s engineers isn’t the ISA. It’s the toolchain. The documentation. The ability to actually get chips. The ability to publish a blog post without it going down.
Subero switched his entire stack from STM32 and ARM to RISC-V — he made a video about it a year ago. He’s a published author with Apress. He’s not a hobbyist. And his website still couldn’t handle the traffic.
The open hardware movement likes to talk about democratizing access to silicon. But the democratization stops at the edge of the first world’s infrastructure. The debate about RISC-V is happening on Hacker News, on Lobsters, on blogs hosted by companies that rate-limit their customers. The people who have the most at stake in the outcome are the ones whose voices are most likely to be throttled.
One engineer in the HN thread noted that the site was showing a rate limit error even for residential connections — it wasn’t the users being throttled, it was the author’s web host throttling the site. The infrastructure of the debate is as fragile as the infrastructure of the hardware.
That’s the real story of this week’s RISC-V argument. Not whether the ISA is elegant. Not whether openness beats elegance. The real story is that the person making the case for openness couldn’t keep his own website open long enough for the first world to read it.
Sources
- A Third World Embedded Engineer Responds to “RISC-V: They Should Have Known Better”
- A Third World Embedded Engineer Responds to “RISC-V: They Should Have Known Better” | Lobsters
- Rate Limit Hit: Embedded Engineer’s RISC-V Response Blocked — A 3rd World Embedded Engineer Responds to “RISC-V They Sh…
- RISC-V: They Should Have Known Better | Lobsters
- RISC-V: They Should Have Known Better