On Friday, Dmitry Grinberg — the engineer behind the dmitry.gr blog — published a sprawling technical autopsy of RISC-V titled “They Should Have Known Better.” By Saturday morning it had 85 points and 224 comments on Hacker News, and the thread was still climbing. The post is a meticulous, section-by-section dismantling of the open instruction set architecture: “Everything for Everyone,” “Optionality,” “Missing Obvious Pieces,” “Ridiculous encoding.” Grinberg’s conclusion, delivered with the weariness of someone who has been asked one too many times to explain his distaste, is that RISC-V’s design-by-committee approach produced an ISA that tries to be all things to all people and ends up being mediocre for everyone.

The conventional read, at least on HN, is that this is a devastating blow. The predictable contrarian read is that the critique proves RISC-V is winning — you don’t get 224-comment threads about irrelevant architectures. Both miss the point.

The Critique Is the Product Working

Grinberg’s core complaint is that RISC-V’s “everything for everyone” philosophy — the optionality, the extensibility, the refusal to make hard choices — is a design flaw. But that’s not a bug. It’s the entire point. RISC-V was never meant to be a single, perfect ISA. It was meant to be a substrate: a common base that can be extended, pruned, and specialized for everything from a $0.10 microcontroller to a datacenter accelerator. The “ridiculous encoding” and “missing obvious pieces” are the cost of that flexibility. Grinberg is judging RISC-V against a standard it explicitly rejected.

But here’s the thing the defenders miss: Grinberg is right that the cost is real. Optionality is not free. Every extension point, every reserved encoding, every “we’ll figure it out later” in the spec is a tax paid by every implementer, forever. The question isn’t whether RISC-V has flaws. It’s whether the flaws are the price of a bet that’s paying off.

The People Who Should Be Grateful

The people who should be most grateful for Grinberg’s post are not RISC-V’s critics. They’re the engineers inside the ecosystem who have been trying to make hard decisions and getting shouted down by the “everything for everyone” consensus. Every standards body has a faction that wants to deprecate bad encodings, pick winners, and stop pretending that optionality is free. That faction has been losing, because the big-tent philosophy is baked into RISC-V’s governance. Grinberg’s post is ammunition for them. It’s a named, respected engineer saying in public what they’ve been saying in private.

One engineer who has spent three years trying to get a deprecated encoding removed from the spec put it this way in a Slack DM: “I’ve been saying this for two years. It took a blog post from someone outside the Foundation for anyone to listen.”

Next week, at Hot Chips 2026 at Stanford, the RISC-V tutorial will feature sessions from SiFive and Canonical on “profiles and platforms” and “architectural convergence on RVA23.” That’s the language of hard choices — profiles, platforms, convergence. It’s the ecosystem’s attempt to do what Grinberg is demanding: stop being everything for everyone and start being something specific for someone. The critique gives that effort cover.

The People Who Should Be Worried

The people who should be worried are not RISC-V’s advocates. They’re the companies that have been marketing RISC-V as a free lunch — “the open alternative to ARM” — without acknowledging the tradeoffs. Nvidia ships a billion RISC-V cores a year, embedded in GPUs and networking chips where the ISA’s flaws don’t matter because the cores are invisible. But the companies selling RISC-V as a general-purpose application processor — the ones competing head-on with ARM’s Cortex line — are the ones who have to live with the “ridiculous encoding” and the “missing obvious pieces.” Grinberg’s critique is a reminder that the free lunch was never free. The bill comes due in verification time, in compiler complexity, in the thousand small decisions that a mature ISA like ARM made decades ago and RISC-V deferred.

That’s not an argument against RISC-V. It’s an argument for honesty about what RISC-V is. The open ISA was never going to be ARM with the serial numbers filed off. It was always going to be a different kind of thing: messier, more flexible, more democratic, and — yes — more flawed. The question is whether the flaws are the kind you can live with, and the answer depends on what you’re building.

The Verdict Is Still Out

Grinberg’s post ends with a section titled “Does This Mean RISC-V is Doomed?” His answer, from the table of contents, appears to be no — but the fact that the question has to be asked, in public, by a named engineer, is itself the story. RISC-V has spent a decade being a movement. Movements don’t get 6,000-word technical autopsies. Engineering projects do. The critique is a sign that RISC-V has crossed a threshold: it’s now important enough to be judged on its merits, not its ideology.

That’s uncomfortable for the true believers, who have been treating the ISA as a cause rather than a tool. It’s also uncomfortable for the European consortium Quintauris, which announced a leadership transition on July 7 and has been positioning itself as the commercial face of the RISC-V ecosystem. The religion is over. The engineering is just beginning — and the people who actually have to ship silicon are the ones who should be relieved.

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